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SMBus/I2C 8-Channel LED Driver
ISL97677
The ISL97677 is an SMBus/I2C controlled multi-channel LED driver for notebook and monitor LCD backlight applications with PWM dimming and fault reporting functions. The ISL97677 is capable of driving typically 96 pieces of 3.4V/50mA LEDs. The ISL97677 has multiple channels of voltage controlled current sources with typical currents matching to 0.7%, which compensate for the non-uniformity effect of forward voltages variance in the LED strings. To minimize the voltage headroom and power loss in the typical multi-string operation, the ISL97677 features dynamic headroom control that monitors the highest LED forward voltage string and uses its feedback signal for output regulation. The ISL97677 can operate in multiple modes of operations. It can be controlled by SMBus/I2C communications and an external PWM dimming signal with currents matching of 1% across all ranges. The ISL97677 features extensive protection functions that include string open and short circuit detections, OVP, and OTP. The fault conditions will be recorded in the Fault/Status register. There are selectable short-circuit thresholds and the switching frequency can be programmed between 500kHz and 1.5MHz. ISL97677 is available in the 32 Leads QFN 5mmx5mm and operate from -40C to +85C with input voltage ranges from 4.75V to 26V.
ISL97677
Features
* 8 Channels * 4.75V ~ 26V Input * 45V Maximum Output * Drive Typically 96 LEDs (3.4V/50mA each) * Dimming Controls - SMBus/I2C 8-Bit PWM Dimming - SMBus and External PWM DPST Dimming Control - External PWM Dimming with or without SMBus/I2C - PWM Dimming range from 0.4% to 100% * Current Matching 0.7% * Protections - String Open Circuit and Short Circuit Detections, OVP, and OTP * Adjustable Dimming Frequency * Adjustable Switching Frequency * 32 Ld (5mmx5mm) QFN Package
Applications
* Notebook Displays WLED or RGB LED Backlighting * LCD Monitor LED Backlighting
November 13, 2009 FN6996.1
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97677
Typical Application Circuit
VIN* = 4.75V~26V L1 10uH/3A Ci 10uF
16
D1 Co 3x4.7uF
8x12 = 96 LEDs Output 45V*, 50mA per string max
ISL97677
LX1 20 VIN VDC VLOGIC OVP
23
LX2 21
806k 100pF 22k
1uF 1uF
18 10
3.3nF
2 3 4 17
SMBCLK/SCL SMBDAT/SDA CH1 PWM EN COMP RSET FSW FPWM AGND AGND AGND AGND AGND AGND PGND PGND
1 19 25 26 27 28 29 30 31 32
CH2 CH3 CH4 CH5 CH6 CH7 CH8
3.3nF 15k
14.2k 50k 333k
14 13 11 12 6 7 8 9 5 15
* Vin > = 12V for 45V/50mA Applications
PGND 22
FIGURE 1. ISL97677 TYPICAL APPLICATION DIAGRAM
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Block Diagram
VIN* = 4.75V~26V 10uH/3A VIN VDC VLOGIC /EN Analog Bias Logic Bias fsw
Fault/Status Register Boost SW
45V*, 50mA per string 96 (8x12) LEDs 2x4.7uF/50V
LX O/P Short
REG1 REG2 OSC & RAMP Comp
OVP
OVP
fSW
=0
Imax
ILIMIT
Logic
FET Drivers
PGND
p e
Fault/Status Control
COMP
GM AMP
Open Ckt, Short Ckt Detects
Highest VF String Detect
VSET + -
CH1 CH2 CH8
1
Temp Sensor
Fault/Status Register
RSET
+ -
REF GEN
+ -
AGND SMBCLK/SCL SMBDAT/SDA
REF_OVP REF_VSC
2
SMBus Interface
* Vin >=12V for 45V/50mA apps
PWMI fPWM
PWM Controller
Mode Select & Dimming Controller
+ -
8
ISL97677
FIGURE 2. ISL97677 BLOCK DIAGRAM
Ordering Information
PART NUMBER ISL97677IRZ (Notes 1, 2) NOTES: 1. Add "-T" or "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97677. For more information on MSL please see techbrief TB363. PART MARKING ISL9767 7IRZ PACKAGE (Pb-free) 32 Ld 5x5 QFN PKG. DWG. # L32.5x5B
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Pin Configuration
ISL97677 (32 LD 5X5 QFN) TOP VIEW
CH8 CH7 CH6 CH5 CH4 CH3 CH2 26 CH1 25 24 NC 23 OVP 22 PGND 21 LX EXPOSED THERMAL PAD AGND AGND AGND AGND 5 6 7 8 9 AGND 10 VLOGIC 11 FSW 12 FPWM 13 RSET 14 COMP 15 AGND 16 VIN 20 LX 19 PGND 18 VDC 17 EN
32 PGND SMBCLK/SCL SMBDAT/SDA PWM 1 2 3 4
31
30
29
28
27
Pin Descriptions
PIN 1, 19, 22 2 3 4 5, 6, 7, 8, 9, 15 10 11 12 13 14 16 17 18 20, 21 23 24 25 ~ 32 NAME PGND SMBCLK/SCL SMBDAT/SDA PWM AGND VLOGIC FSW FPWM RSET COMP VIN EN VDC LX OVP NC CH1 ~ CH8
(I = Input, O = Output, S = Supply) DESCRIPTION Power Ground SMBus/I2C Serial Clock Input SMBus/I2C Serial Data Input and Output PWM Brightness Control Analog Ground Internal 2.5V Logic Bias Regulator. Need Decoupling Capacitor for Regulation When RfSW is 100k, fSW is 500kHz. When RfSW is 33k, fSW is 1.5MHz When RFPWM is 333k, FPWM is 200Hz. When RFPWM is 3.3k, FPWM is 20kHz. Resistor Connection for Setting LED Current Boost compensation Main Power Enable Internal 5V Analog Bias Regulator. Needs Decoupling Capacitor for Regulation Boost MOSFET Drain Terminal Switching Node Overvoltage Protection Input as well as Output Voltage FB Monitoring No Connect LED Driver PWM Dimming Monitoring
TYPE S I I/O I S O I I I O S I S O I I/O I
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Absolute Maximum Ratings
voltage ratings are all with respect to AGND pin VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.75V VDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V COMP, RSET, FPWM, FSW . . . . . . . . . . . . . . . . -0.3V to min . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VDC + 0.3V, 5.75V) SMBCLK, SMBDAT, PWM . . . . . . . . . . . . . . . -0.3V to 5.75V CH1 - CH8, LX, OVP . . . . . . . . . . . . . . . . . . . . -0.3V to 45V PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 3 PSIJT (C/W) 32 Ld QFN (Notes 4, 5) . . . . . . . . . 31 Thermal Characterization (Typical, Note 6)
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . -40C to +85C
32 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 Maximum Continuous Junction Temperature . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . -65C to +150C Power Dissipation TA < +25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2W TA < +70C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8W TA < +85C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W TA < +100C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8W Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 6. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die junction temperature can be estimated more accurately than the JC and JC thermal resistance ratings.
Electrical Specifications
5.
All specifications below are characterized at TA = -40C to +85C; VIN = 12V, /SHUT = 5V, ISET = 36k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. DESCRIPTION CONDITION MIN (Note 7) TYP MAX (Note 7) UNIT
PARAMETER GENERAL VIN IVIN_SHDN VOUT VUVLO VUVLO_HYS
Backlight Supply Voltage VIN Shutdown Current Output Voltage Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis /SHUT = 0
4.75
26 (Note 8) 5 45
V A V V mV
2.9 300
3.3
LINEAR REGULATOR VDC VDC_DROP IVDC VLOGIC VLOGIC_DROP 5V Analog Bias Regulator VDC LDO Dropout Voltage Active Current 2.5V Logic Bias Regulator VLOGIC LDO Dropout Voltage VIN > 6V IVDC = 30mA /SHUT = 5V, R = 33k VIN > 6V IVLOGIC = 30mA 2.3 4.8 5 71 10 2.4 31 2.5 100 5.1 100 V mV mA V mV
BOOST SWITCHING REGULATOR SS SWILimit rDS(ON) Soft-Start Boost FET Current Limit Internal Boost Switch ON-Resistance TA = +25C to +85C 3.0 130 16 4.7 ms A m
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Electrical Specifications
All specifications below are characterized at TA = -40C to +85C; VIN = 12V, /SHUT = 5V, ISET = 36k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) DESCRIPTION Peak Efficiency CONDITION VIN = 24V, 96LEDs, 20mA each, L = 10H with DCR 100m, fSW = 600kHz, TA = +25C VIN = 12V, 96 LEDs, 20mA each, L = 10H with DCR 100m, fSW=600kHz, TA = +25C VIN = 6V, 96 LEDs, 20mA each, L = 10H with DCR 100m, fSW = 600kHz, TA = +25C VIN = 24V, 80 LEDs, 40mA each, L = 10H with DCR 100m, fSW = 600kHz, TA = +25C VIN = 12V, 80 LEDs, 40mA each, L = 10H with DCR 100m, fSW = 600kHz, TA = +25C DMAX DMIN fSW Boost Maximum Duty Cycle Boost Minimum Duty Cycle Boost Switching Frequency fSW = 500kHz fSW = 500kHz Rfsw = 100k Rfsw = 33k ILX_leakage REFERENCE IMATCH IACC Channel-to-Channel Current Matching Absolute Current Accuracy ILED = 20mA IRSET = 36k, TA = +25C IRSET = 36k, TA = -40C to +80C FAULT DETECTION VSC Channel Short Circuit Threshold SMBus Register0x0F, SC[1:0] = 01 SMBus Register0x0F, SC[1:0] = 10 SMBus Register0x0F, SC[1:0] = 11 Vtemp Vtemp_acc VOVP Over-Temperature Threshold Over-Temperature Threshold Accuracy Overvoltage Limit on OVP Pin 1.18 2.4 3.3 4.2 150 5 1.22 1.24 3.6 4.6 5.6 V V V C C V -1.1 -1.5 -2 0.7 +1.1 +1.5 +2 % % % Lx Leakage Current VLX = 45V, /SHUT = 0V 0.45 1.35 0.5 1.5 90 10 0.55 1.65 10 MIN (Note 7) TYP 92.4 MAX (Note 7) UNIT %
PARAMETER Eff_peak
91.5
%
81.6
%
93.4
%
90.7
%
% % MHz MHz A
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Electrical Specifications
All specifications below are characterized at TA = -40C to +85C; VIN = 12V, /SHUT = 5V, ISET = 36k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) DESCRIPTION CONDITION MIN (Note 7) TYP MAX (Note 7) UNIT
PARAMETER
SMBus INTERFACE (SMBus Mode, 1D_EN = 0) VIL VIH VOL Logic Input Low Voltage - SMBCLK/SCL, SMBDAT/SDA Logic Input High Voltage - SMBCLK/SCL, SMBDAT/SDA SMBus Data Line Logic Low Voltage with 1.1k series resistor from data bus to SMBDAT pin IPULLUP = 350A 1.5 0.8 5.5 0.4 V V V
SMBus Data Line Logic Low Voltage without IPULLUP = 4mA series resistor from data bus to SMBDAT pin SMBus TIMING SPECIFICATIONS fSMB tBUF tHD:STA SMBus Clock Frequency Bus Free Time Between Stop and Start Condition Hold Time After (Repeated) START Condition. After this Period, the First Clock is Generated Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time (Note 9) Data Setup Time (Note 9) Clock Low Period Clock High Period Clock/Data Fall Time (Note 9) 4.7 4.0
0.17
V
250
kHz s s
tSU:STA tSU:STO tHD:DAT tSU:DAT tLOW tHIGH tF
4.7 4.0 300 250 4.7 4.0 300
s s ns ns s s ns
CURRENT SOURCES VHEADROOM VISET ILEDmax Dominant Channel Current Source Headroom at CH Pin Voltage at ISET Pin Maximum LED Current per Channel LED config = 8P10S with VF = 3.4V and VIN = 11V ILED = 50mA TA = +25C 1.18 1.0 1.21 50 1.24 V V mA
PWM GENERATOR FPWM Generated PWM Frequency RFPWM = 330k RFPWM = 3.3k Dimming Range VFSW FPWMI VFPWM NOTES: 7. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 8. At maximum VIN of 26V, minimum VOUT is 28V. Minimum VOUT can be lower at lower VIN 9. Limits established by characterization and are not production tested. PWM Dimming Duty Cycle Limits (Note 9) FSW Voltage PWMI Input Frequency Range (Note 9) VFPWM Voltage RFPWM = 3.3k fPWM 30kHz RFSW = 33k 180 18 0.4 1.18 200 1.18 1.21 1.21 200 20 220 22 100 1.24 20k 1.25 Hz kHz % V Hz V
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Typical Performance Curves
100 95 EFFICIENCY (%) 90 85 80 75 70 +25C 50mA 8P11S fSW = 600kHz EFFICIENCY (%) 0C +85C -40C 100 95 90 85 80 75 70 20mA 8P11S fSW = 600kHz 0C +85C -40C
+25C 0 5 10 15 VIN (V) 20 25 30
0
5
10
15 VIN (V)
20
25
30
FIGURE 3. EFFICIENCY vs VIN vs TEMPERATURE AT 50mA
100 95 90 85 80 75 70 65 60 55 50 45 40 35 30
FIGURE 4. EFFICIENCY vs VIN vs TEMPERATURE AT 20mA
95 94 93
EFFICIENCY (%)
8P10S
50mA 8P11S
EFFICIENCY (%)
12V/50mA
92 91 90 89 88 87 86 85 84 400
24V
24V/50mA
12V
0
10
20 30 ILED (mA)
40
50
600 800 1k 1.2k 1.4k SWITCHING FREQUENCY (Hz)
1.6k
FIGURE 5. EFFICIENCY vs ILED
FIGURE 6. EFFICIENCY vs SWITCHING FREQUENCY
1.0 CURRENT MATCHING (%) 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0
CURRENT MATCHING (%)
20mA - 8P12S 50mA - 8P11S 12V/20mA
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0
50mA 8P11 0C
+25C +85C
12V/50mA
-40C 5 10 15 VIN (V) 20 25 30
1
2
3
4 5 CHANNEL
6
7
8
FIGURE 7. CHANNEL-TO-CHANNEL CURRENT MATCHING EXAMPLE
FIGURE 8. CURRENT MATCHING vs VIN vs TEMPERATURE
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Typical Performance Curves (Continued)
2.0 1.8 1.6 1.4 ILED (mA) 1.2 1.0 0.8 0.6 0.4 0.2 24V/20mA 5V/20mA 20mA - 8P12S 50mA - 8P11S 12V/50mA 24V/50mA CHANNEL VOLTAGE (V) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1 2 12V/20mA HEADROOM CONTROL CHANNEL 3 4 5 CHANNEL 6 7 8 12V/50mA 20mA - 8P12S 50mA - 8P11S
0.0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 PWM DIMMING DUTY CYCLE (%)
FIGURE 9. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING DUTY CYCLE
FIGURE 10. TYPICAL CHANNEL VOLTAGE EXAMPLE
1.00 0.95 0.90 VHEADROOM (V)
50mA 8P11S
1.0 +25C 0.9 0.8 VHEADROOM (V) 0.7 0.6 0.5 0.4 0.3 0.2 0.1
20mA 8P11S +85C
0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0 5 10 15 VIN (V) 20 25 30 0C +85C
+25C
0C
0.0
0
5
10
15 VIN (V)
20
25
30
FIGURE 11. VHEADROOM vs VIN vs TEMPERATURE AT 50mA
FIGURE 12. VHEADROOM vs VIN vs TEMPERATURE AT 20mA
10 9 8 IIN (mA) 7 6 5 4 3 2 1 0 0
/SHUT = HIGH PWM DUTY CYCLE = 0% LX (20V/DIV) +85C VO (100mV/DIV) -40C ILED (20mA/DIV)
5
10
15 VIN (V)
20
25
30
FIGURE 13. QUIESCENT CURRENT vs VIN vs TEMPERATURE WITH /SHUT ENABLE
FIGURE 14. VOUT RIPPLE VOLTAGE
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Typical Performance Curves (Continued)
VO (20V/DIV) EN (5V/DIV) VO (20V/DIV) EN (5V/DIV)
IIN (1A/DIV) IIN (1A/DIV)
ILED (50mA/DIV)
ILED (50mA/DIV)
FIGURE 15. IN-RUSH CURRENT and LED CURRENT AT VIN = 12V
FIGURE 16. IN-RUSH CURRENT AND LED CURRENT AT VIN = 26V
VIN (10V/DIV)
VIN (10V/DIV) IIN (500mA/DIV)
IIN (500mA/DIV)
ILED (50mA/DIV)
ILED (50mA/DIV)
FIGURE 17. LINE REGULATION WITH VIN CHANGES FROM 12V TO 26V DISABLE PROFILE
FIGURE 18. LINE REGULATION WITH VIN CHANGES FROM 26V TO 12V
VO (1V/DIV) VO (1V/DIV)
ILED (20mA/DIV)
ILED (20mA/DIV)
FIGURE 19. LOAD REGULATION WITH ILED CHANGES FROM 0.4% TO 100% PWM DIMMING
FIGURE 20. LOAD REGULATION WITH ILED CHANGES FROM 100% TO 0.4% PWM DIMMING
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Typical Performance Curves (Continued)
VO (1V/DIV)
VO (500mV/DIV)
ILED (20mA/DIV) ILED (20mA/DIV)
FIGURE 21. LOAD REGULATION WITH ILED CHANGES FROM 0% TO 100% PWM DIMMING
FIGURE 22. LOAD REGULATION WITH ILED CHANGES FROM 100% to 0% PWM DIMMING
VO (20V/DIV) EN (5V/DIV)
IIN (1A/DIV)
ILED (50mA/DIV)
FIGURE 23. DISABLE PROFILE
Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the minimal voltage needed to enable the LED string with the highest forward voltage drop to run at the programmed current. The ISL97677 employs current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. Such architecture achieves a fast transient response that is essential for the notebook backlight application where the power can be several Li-ion cell batteries or instantly change to an AC/DC adapter without rendering a noticeable visual nuisance. The number of LEDs that can be driven by ISL97677 depends on the type of LED chosen in the application. The ISL97677 is capable of boosting up to 45V and drive 8 channels of LEDs at maximum of 45mA per channel.
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the current source circuit, as shown in Figure 24. The LED peak current is set by translating the RSET current to the output with a scaling factor of 707.9/RSET. The source terminals of the current source MOSFETs are designed to run at 500mV to optimize power loss vs accuracy requirements. The sources of errors of the channel-to-channel current matching come from the op amps offset, internal layout, reference, and current source resistors. These parameters are optimized for current matching and absolute current accuracy. However, the absolute accuracy is additionally determined by the external RSET. A 0.1% tolerance resistor is recommended.
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.
The ratio of the OVP capacitors should be the inverse of the OVP resistors. For example, if RUPPER/RLOWER = 33/1, then CUPPER/CLOWER=1/33 with CUPPER = 100pF and CLOWER = 3.3nF.
Dimming Controls
The ISL97677 allows two ways of controlling the LED current, and therefore, the brightness. They are:
+ REF
1. DC current adjustment 2. PWM chopping of the LED current defined in Step 1. There are various ways to achieve DC or PWM current control, which will be described in the following.
+ -
+ RSET
PWM DIMMING
In any dimming controls, the EN pin must be high. EN is a high voltage pin that can be applied with a digital signal or tied directly to VIN for enable function. MAXIMUM DC CURRENT SETTING The initial brightness should be set by choosing an appropriate value for RSET. This should be chosen to fix the maximum possible LED current:
707.9 I LEDmax = -------------R SET (EQ. 2)
FIGURE 24. SIMPLIFIED CURRENT SOURCE CIRCUIT
Dynamic Headroom Control
The ISL97677 features a proprietary Dynamic Headroom Control circuit that detects the highest forward voltage string or effectively the lowest voltage from any of the CH pins. When this lowest IIN voltage is lower than the short circuit threshold, VSC, such voltage will be used as the feedback signal for the boost regulator. The boost makes the output to the correct level such that the lowest CH pin is at the target headroom voltage. Since all LED strings are connected to the same output voltage, the other CH pins will have a higher voltage, but the regulated current source circuit on each channel will ensure that each channel has the same programmed current. The output voltage will regulate cycle by cycle and is always referenced to the highest forward voltage string in the architecture.
Alternatively, the RSET can be replaced by digital potentiometer for adjustable current. On the other hand, the current accuracy is designed when RSET is set at 20m to 40mA. PWM CONTROL The ISL97677 also provides PWM dimming by PWM chopping of the current in the LEDs for all 8 channels to provide an average LED current. During the On periods, the LED current will be defined by the value of RSET, as described in Equation 1. PWM Dimming Frequency Adjustment The dimming frequencies of all modes are set by an external resistor at the FPWM pin as shown in Equation 3:
6.66 x10 f PWM = ----------------------RPWM
7
OVP and VOUT Requirement
The Overvoltage Protection (OVP) pin has a function of setting the overvoltage trip level as well as limiting the VOUT regulation range. The ISL97677 OVP threshold is set by RUPPER and RLOWER as shown in Equation 1:
V OUT_OVP = 1.21V x ( R UPPER + R LOWER ) R LOWER (EQ. 1)
(EQ. 3)
VOUT can only regulate between 64% and 100% of the VOUT_OVP such that: Allowable VOUT = 64% to 100% of VOUT_OVP For example, if 10 LEDs are used with the worst case VOUT of 35V. If R1 and R2 are chosen such that the OVP level is set at 40V, then the VOUT is allowed to operate between 25.6V and 40V. If the requirement is changed to a 6 LEDs 21V VOUT application, then the OVP level must be reduced and users should follow VOUT = (64% ~100%)OVP requirement. Otherwise, the headroom control will be disturbed such that the channel voltage can be much higher than expected and sometimes it can prevents the driver from operating properly. 12
where fPWM is the desirable PWM dimming frequency and RFPWM is the setting resistor. External PWM Dimming The ISL97677 can operate as basic PWM dimming LED driver with or without the need of SMBus/I2C interface. To do so, users need to set EN = high and SMBCLK/SCL = grounded or floating, SMBDAT/SDA = grounded or floating. The EN is a high voltage pin that can be applied with a digital I/O signal or tie to VIN. The PWM output will follow the PWM input and the dimming frequency will be set by RPWM.
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Switching Frequency
The boost switching frequency can be adjusted by a resistor as shown in Equation 4:
( 5 x10 ) f SW = ----------------------R OSC
10
prevents apparent faults during these transient events from allowing any of the LED strings to fault out. See Table 1 for more details.
(EQ. 4)
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on each channel and disables faulty channels which are detected above the programmed short circuit threshold. There are three selectable levels of short circuit threshold (3V, 4V, and 5V) that can be programmed through the Configuration Register 0x0F. When an LED becomes shorted, the action taken is described in Table 1. The default short circuit threshold is 4V. The detection of this failure mode can be disabled by SMBus interface via Register 0x0F.
where fSW is the desirable boost switching frequency and ROSC is the setting resistor.
5V and 2.3V Low Dropout Regulators
A 5V LDO regulator is present at the VDC pin to develop the necessary low voltage supply, which is used by the chips internal control circuitry. Because VDC is an LDO pin, it requires a bypass capacitor of 1F or more for the regulation. The VDC pin can be used for a coarse regulator or reference but do not pull more than few mA from it. Similarly, a 2.3V LDO regulator is present at the VLOGIC pin to develop the necessary low voltage supply for the chip's internal logic control circuitry. A 1F bypass capacitor or more is needed for regulation. The VLOGIC pin can be used as a coarse regulator or reference but do not pull more than few mA from it.
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. The ISL97677 monitors the current in each channel such that any string which reaches the intended output current is considered "good". Should the current subsequently fall below the target, the channel will be considered an "open circuit". Furthermore, should the boost output of the ISL97677 reach the OVP limit or should the lower over-temperature threshold be reached, all channels which are not "good" will immediately be considered as "open circuit". Detection of an "open circuit" channel will result in a time-out before disabling of the affected channel. Some users employ some special types of LEDs that have zener diode structure in parallel with the LED for ESD enhancement, thus enabling open circuit operation. When this type of LED goes open circuit, the effect is as if the LED forward voltage has increased, but no light will be emitted. Any affected string will not be disabled, unless the failure results in the boost OVP limit being reached, allowing all other LEDs in the string to remain functional. Care should be taken in this case that the boost OVP limit and SCP limit are set properly, so as to make sure that multiple failures on one string do not cause all other good channels to be faulted out. This is due to the increased forward voltage of the faulty channel making all other channel look as if they have LED shorts. See Table 1 for details for responses to fault conditions.
Soft-Start
The ISL97677 uses a digital soft-start where the boost current limit is stepped up in 8 steps. The initial current limit level is set to one ninth of the full current limit, with subsequent steps increasing this by a ninth every 2ms. In the event that no LEDs have been conducting during the interval since the last step (for example, if the LEDs are running at low duty cycle at low PWM frequency) then the step will be delayed until the LEDs are conducting. If the LEDs are disabled and re-enabled again then soft start will be restarted when the LEDs are enabled.
Fault Protection and Monitoring
The ISL97677 features extensive protection functions to cover all the perceivable failure conditions. The failure mode of a LED can be either open circuit or as a short. The behavior of an open circuited LED can additionally take the form of either infinite resistance or, for some LEDs, a zener diode, which is integrated into the device in parallel with the now opened LED. For basic LEDs (which do not have built-in zener diodes), an open circuit failure of an LED will only result in the loss of one channel of LEDs without affecting other channels. Similarly, a short circuit condition on a channel that results in that channel being turned off does not affect other channels unless a similar fault is occurring. All LED faults are reported via the SMBus interface to Register 0x02 (Fault/Status register). Due to the lag in boost response to any load change at its output, certain transient events (such as significant step changes in LED duty cycle) can transiently look like LED fault modes. The ISL97677 uses feedback from the LEDs to determine when it is in a stable operating region and
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage and keeps the voltage at a safe level. The OVP threshold is set as shown in Equation 5:
OVP = 1.21V x ( R UPPER + R LOWER ) R LOWER (EQ. 5)
These resistors should be large to minimize the power loss. For example, a 1Mk RUPPER and 30k RLOWER sets OVP to 41.2V. Large OVP resistors also allow COUT discharges slowly during the PWM Off time. Parallel capacitors should be placed across the OVP resistors such that RUPPER/RLOWER = CLOWER/CUPPER. Using a CUPPER value of at least 30pF is recommended. These
FN6996.1 November 13, 2009
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ISL97677
capacitors reduce the AC impedance of the OVP node, which is important when using high value resistors. upper threshold will also set the thermal fault bit of the Fault/Status register 0x02. Unless disabled via the /SHUT pin, the device stays in an active state throughout, allowing the external processor to interrogate the fault condition. For the extensive fault protection conditions, please refer to Figure 25 and Table 1 for details.
Undervoltage Lockout
If the input voltage falls below the UVLO level of 2.8V, the device will stop switching and be reset. Operation will restart only if the device control interface re-enables it once the input voltage is back in the normal operating range. Also all digital settings will be reset to their default states.
Shutdown
When the EN pin is low the entire chip is shut down to give close to zero shutdown current. The digital interfaces will not be active during this time.
Over-Temperature Protection (OTP)
The ISL97677 includes two over-temperature thresholds. The lower threshold is set to +130C. When this threshold is reached, any channel which is outputting current at a level significantly below the regulation target will be treated as "open circuit" and disabled after a time-out period. The intention of the lower threshold is to allow bad channels to be isolated and disabled before they cause enough power dissipation (as a result of other channels having large voltages across them) to hit the upper temperature threshold. The upper threshold is set to +150C. Each time this is reached, the boost will stop switching and the output current sources will be switched off and stay off until the control interface disables and re-enables it. Hitting of the
VIN LX
VOUT
DRIVER
FAULT
O/P SHORT FET DRIVER
LX OVP
IMAX ILIMIT
LOGIC
VSC
CH1
VSET/2 REG THRM SHDN
CH8
REF T2 TEMP SENSOR T1 VSET + Q1 VSET + PWM8/OC8/SC8 Q8
OTP
PWM1/OC1/SC1 FAULT/ STATUS REGISTER SMBUS CONTROL LOGIC
DC CURRENT
FIGURE 25. SIMPLIFIED FAULT PROTECTIONS
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ISL97677
TABLE 1. PROTECTIONS TABLE VOUT REGULATED BY Highest VF of CH2 through CH8
CASE 1
FAILURE MODE CH1 Short Circuit
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS ACTION CH2 through CH8 Normal
Upper CH1 ON and burns power Over-Temperature Protection limit (OTP) not triggered and VIIN0 < VSC Upper OTP triggered but VIN1 < VSC Upper OTP not triggered but VIIN1 > VSC Upper OTP not triggered and VIIN1 < VSC CH1 goes off
2
CH1 Short Circuit
Same as CH1
Highest VF of CH2 through CH8
3
CH1 Short Circuit
CH1 disabled after 6 PWM cycles time-out.
Highest VF of If 3 channels are already shut down, all channels will CH2 through CH8 be shut down. Otherwise CH2-8 will remain as normal Highest VF of CH2 through CH8 VF of CH1
4
CH1 Open Circuit with infinite resistance CH1 LED Open Circuit but has paralleled Zener CH1 LED Open Circuit but has paralleled Zener CH1 LED Open Circuit but has paralleled Zener
VOUT will ramp to OVP. CH1 will CH2 through CH8 Normal time-out after 6 PWM cycles and switch off. VOUT will drop to normal level. CH2 through CH8 ON, Q2 through Q8 burn power Same as CH1
5
Upper OTP not CH1 remains ON and has triggered and VIIN1 < highest VF, thus VOUT VSC increases Upper OTP triggered but VIIN1 < VSC CH1 goes off
6
VF of CH1
7
CH1 OFF Upper OTP not triggered but VIIN1 > VSC CH1 remains ON and has Upper OTP not triggered but VIINx > highest VF, thus VOUT VSC increases.
CH2 through CH8 Normal
Highest VF of CH2 through CH8 VF of CH1
VOUT increases then CH-X switches OFF. This is an unwanted shut off and can be prevented by setting OVP and/or VSC at an appropriate level.
8
Channel-toChannel VF too high Channel-toChannel VF too high Output LED string voltage too high VOUT/LX shorted to GND
Lower OTP triggered but VIINx < VSC Upper OTP triggered but VIINx < VSC VOUT > VOVP
Any channel at below the target current will fault out after 6 PWM cycles. Remaining channels driven with normal current. All channels switched off
Highest VF of CH1 through CH8 Highest VF of CH1 through CH8 Highest VF of CH1 through CH8
9
10
Driven with normal current. Any channel that is below the target current will time-out after 6 PWM cycles. LX will not switch
11
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SMBCLK VIH VIL
tLOW
tR
tF
tHD:STA SMBDAT VIH VIL tBUF
tHD:DAT
tHIGH tSU:DAT
tSU:STA
tSU:STO
P
S
S
P
NOTES: SMBus Description S = Start condition P = Stop condition A = Acknowledge A = Not acknowledge R/W = Read enable at high; Write enable at low
FIGURE 26. SMBUS INTERFACE
1 S
7 SLAVE ADDRESS Master to Slave Slave to Master
1 W
1 A
8 COMMAND CODE
1 A
8 DATA BYTE
1 A
1 P
FIGURE 27. WRITE BYTE PROTOCOL
1 S
7 SLAVE ADDRESS Master to Slave Slave to Master
1 W
1 A
8 COMMAND CODE
1 A
1 S
8 SLAVE ADDRESS
1 R
1 A
8 DATA BYTE
1 A
1 P
FIGURE 28. READ BYTE PROTOCOL
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Write Byte
The Write Byte protocol is only three bytes long. The first byte starts with the slave address followed by the "command code," which translates to the "register index" being written. The third byte contains the data byte that must be written into the register selected by the "command code". A shaded label is used on cycles during which the slaved backlight controller "owns" or "drives" the Data line. All other cycles are driven by the "host master." confusion. Therefore, if the device is in the write mode where bit 0 is 0, the slave address byte is 0x58 or 01011000b. If the device is in the read mode where bit 0 is 1, the slave address byte is 0x59 or 01011001b. The backlight controller may sense the state of the pins at POR or during normal operation--the pins will not change state while the device is in operation.
MSB LSB
Read Byte
As shown in the Figure 28, the four byte long Read Byte protocol starts out with the slave address followed by the "command code" which translates to the "register index." Subsequently, the bus direction turns around with the rebroadcast of the slave address with bit 0 indicating a read ("R") cycle. The fourth byte contains the data being returned by the backlight controller. That byte value in the data byte reflects the value of the register being queried at the "command code" index. Note the bus directions, which are highlighted by the shaded label that is used on cycles during which the slaved backlight controller "owns" or "drives" the Data line. All other cycles are driven by the "host master."
0
1
0
1
1
0
0
R/W
FIGURE 29. SLAVE ADDRESS BYTE DEFINITION
SMBus Register Definitions
The backlight controller registers are Byte wide and accessible via the SMBus Read/Write Byte protocols. Their bit assignments are provided in the following sections with reserved bits containing a default value of "0".
Slave Device Address
The slave address contains 7 MSB plus one LSB as R/W bit, but these 8 bits are usually called Slave Address bytes. As shown in Figure 29, the high nibble of the slave address byte is 0x5 or 0101b to denote the "backlight controller class." Bit 3 in the lower nibble of the slave address byte is 1. Bit 0 is always the R/W bit, as specified by the SMBus protocol. Note: In this document, the device address will always be expressed as a full 8-bit address instead of the shorter 7-bit address typically used in other backlight controller specifications to avoid
TABLE 2A. REGISTER LISTING
ADDRESS 0x00 0x01 0x02 0x03 REGISTER PWM Brightness Control Register Device Control Register Fault/Status Register Identification Register BIT 7 BRT7 Reserved Reserved LED PANEL BIT 6 BRT6 Reserved Reserved MFG3 BIT 5 BRT5 Reserved 2_CH_SD MFG2 BIT 4 BRT4 Reserved 1_CH_S D MFG1 BIT 3 BRT3 Reserved BL_STAT MFG0 BIT 2 BRT2 PWM_MD BIT 1 BRT1 PWM_SEL BIT 0 BRT0 BL_CTL FAULT REV0 DEFAULT VALUE 0xFF 0x00 0x00 0xC8 SMBUS PROTOCOL Read and Write Read and Write Read Only Read Only
OV_CURR THRM_SHDN REV2 REV1
17
RE AD /W RI TE
FN6996.1 November 13, 2009
DEVICE IDENTIFIER
DEVICE ADDRESS
BI T
ISL97677
TABLE 2B. DATA BIT DESCRIPTIONS ADDRESS 0x00 0x01 REGISTER PWM Brightness Control Register Device Control Register DATA BIT DESCRIPTIONS BRT[7..0] = 256 steps of DPWM duty cycle brightness control PWM_MD = PWM mode select bit (1 = absolute brightness, 0 = % change), default = 0 PWM_SEL = Brightness control select bit (1 = control by PWMI, 0 = control by SMBus), default = 0 BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0 PWM_MD PWM_SEL X 1 0 1 0 0 PWMI Mode SMBus Mode SMBus and PWMI mode with DPST MODE
0x02
Fault/Status Register
2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK) 1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK) BL_STAT = BL status (1 = BL On, 0 = BL Off) OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK) THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK) FAULT = Fault occurred (Logic "OR" of all of the fault conditions) MFG[3..0] = Manufacturer ID (16 vendors available. Intersil is vendor ID 9) REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins)
0x03
Identification Register
PWM Brightness Control Register (0x00)
The Brightness control resolution has 256 steps of PWM duty cycle adjustment. The bit assignment is shown in Tables 2A and 2B. All of the bits in this Brightness Control Register can be read or write. Step 0 corresponds to the minimum step where the current is less than 10A. Steps 1 to 255 represent the linear steps between 0.39% and 100% duty cycle with approximately 0.39% duty cycle adjustment per step. * An SMBus Write Byte cycle to Register 0x00 sets the PWM brightness level only if the backlight controller is in SMBus mode (see Table 3 "Operating Modes selected by Device Control Register Bits 1 and 2"). * An SMBus Read Byte cycle to Register 0x00 returns the programmed PWM brightness level, regardless of the value of PWM_SEL. * An SMBus setting of 0xFF for Register 0x00 sets the backlight controller to the maximum brightness. * An SMBus setting of 0x00 for Register 0x00 sets the backlight controller to the minimum brightness output in which the LED current is guaranteed to be less than 10A. * Default value for Register 0x00 is 0xFF.
unless otherwise written. Bits 7 and 6 are not implemented and will always read low.
TABLE 3. OPERATING MODES SELECTED BY DEVICE CONTROL REGISTER BITS 1 AND 2 PWM_MD PWM_SEL X 1 0 1 0 0 PWMI Mode SMBus Mode SMBus and PWMI Mode with DPST MODE
The PWM_SEL bit determines whether the SMBus or PWMI input should drive the output brightness in terms of PWM dimming. When PWM_SEL bit is 1, the PWMI drives the output brightness regardless of what the PWM_MD is. When the PWM_SEL bit is 0, the PWM_MD bit selects the manner in which the PWM dimming is to be interpreted; when this bit is 1, the PWM dimming is based on the SMBus brightness setting. When this bit is 0, the PWM dimming reflects a percentage change in the current brightness programmed in the SMBus Register 0x00, i.e. DPST (Display Power Saving Technology) mode, as shown in Equation 6:
DPST Brightness = Cbt x PWMI (EQ. 6)
Device Control Register (0x01)
This register has 2 bits that control the operating mode of the backlight controller and a single bit that controls the BL ON/OFF state. The remaining bits are reserved. The bit assignment is shown in Tables 2A and 2B. All other bits in the Device Control Register will read as low
Where: Cbt = Current brightness setting from SMBus Register 0x00 without influence from the PWMI PWMI = is the percent duty cycle of the PWMI
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For example, the Cbt = 50% duty cycle programmed in the SMBus Register 0x00 and the PWM frequency is tuned to be 200Hz with an appropriate capacitor at the FPWM pin. On the other hand, PWMI is fed with a 1kHz 30% high PWM signal. When PWM_SEL = 0 and PWM_MD = 0, the device is in DPST operation where DPST brightness = 15% PWM dimming at 200Hz. * All reserved bits return a "0" when read. * All reserved bits have no functional effect when written. * All defined control bits return their current, latched value when read. * A value of 1 written to BL_CTL turns on the BL in 4ms or less after the write cycle completes. The BL is deemed to be on when Bit 3 BL_STAT of Register 0x02 is 1 and Register 0x09 is not 0. See Tables 2A and 2B. * A value of 0 written to BL_CTL immediately turns off the BL. The BL is deemed to be off when Bit 3 BL_STAT of Register 0x02 is 0 and Register 0x09 is 0. See Tables 2A and 2B. * **Note that the behavior of Register 0x00 (Brightness Control Register) is affected by certain combinations of the control bits, as shown in Table 3 "Operating Modes Selected by Device Control Register Bits 1 and 2." * When an SMBus mode is selected, Register 0x00 reflects the last value written to it. But, when any non-SMBus mode is selected, Register 0x00 reflects the current brightness value based on the current mode of operation, with the exception of SMBus mode with DPST, where PWM_MD = 0 and PWM_SEL = 0. * When SMBus mode with DPST is selected, Register 0x00 reflects the last value written to it from SMBus. * When a write to Register 0x01 (Device Control Register) causes the backlight controller to transition to an SMBus mode, the brightness of the BL does not change. On the other hand, when a write to Register 0x01causes the backlight controller to transition to a non-SMBus mode, the brightness of the BL changes as appropriate for the new mode. * The default value for Register 0x01 is 0x00. read-only, with the exception of bit 0, which can be cleared by writing to it. * A Read Byte cycle to Register 0x02 indicates the current BL on/off status in BL_STAT (1 if the BL is on, 0 if the BL is off). * A Read Byte cycles to Register 0x2 also returns FAULT as the logical OR of THRM_SHDN, OV_CURR, 2_CH_SD, and 1_CH_SD should these events occur. * 1_CH_SD returns a 1 if one or more channels have faulted out. * 2_CH_SD returns a 1 if two or more channels have faulted out. * A fault will not be reported in the event that the BL is commanded on and then immediately off by the system. * When FAULT is set to 1, it will remain at 1 even if the signal which sets it goes away. FAULT will be cleared when the BL_CTL bit of the Device Control Register is toggled or when written low. At that time, if the fault condition is still present or reoccurs, FAULT will be set to 1 again. BL_STAT will not cause FAULT to be set. * The controller will not indicate a fault if the VBL+ goes away, whether or not the LEDs were on at the time of the power loss. This can occur if there is some hang condition that causes the user to force the system off by holding the power button down for 4s. * The default value for Register 0x02 is 0x00.
Identification Register (0x03)
The ID register contains 3-bit fields to denote the LED driver (always set to 1), manufacturer and the silicon revision of the controller IC. The bit field widths allow up to 16 vendors with up to 8 silicon revisions each. In order to keep the number of silicon revisions low, the revision field will not be updated unless the part will make it out to the user's factory. Thus, if during the engineering development process, 3 silicon spins were needed, the next available revision ID would be used for all 3 spins until that same ID made it to the factory. Except Bit 7, which has to be 1, all of the bits in this register are read-only. * Vendor ID 9 represents Intersil Corporation. * The default value for Register 0x03 is 0xC8. The initial value of REV shall be 0. Subsequent values of REV will increment by 1.
Fault/Status Register (0x02)
This register has 6 status bits that allow monitoring of the backlight controller's operating state. Bit 0 is a logical "OR" of all fault codes to simplify error detection. Not all of the bits in this register are fault related (Bit 3 is a simple BL status indicator). The remaining bits are reserved and return a "0" when read and ignore the bit value when written. All of the bits in this register are
Components Selections
According to the inductor Voltage-Second Balance principle, the change of inductor current during the switching regulator On-time is equal to the change of inductor current during the switching regulator Off-time.
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Since the voltage across an inductor is as shown in Equation 7:
V L = L x I L t (EQ. 7)
It is recommended that an input capacitor of at least 10F be used. Ensure the voltage rating of the input capacitor is suitable to handle the full supply range.
Inductor
(EQ. 8)
and IL @ On = IL @ Off, therefore:
( V I - 0 ) L x D x tS = ( VO - VD - VI ) L x ( 1 - D ) x tS
where D is the switching duty cycle defined by the turn-on time over the switching periods. VD is Schottky diode forward voltage that can be neglected for approximation. Rearranging the terms without accounting for VD gives the boost ratio and duty cycle respectively as Equations 9 and 10:
VO VI = 1 ( 1 - D ) D = ( VO - VI ) VO (EQ. 9) (EQ. 10)
The selection of the inductor should be based on its maximum and saturation current (ISAT) characteristics, power dissipation (DCR), EMI susceptibility (shielded vs unshielded), and size. Inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance and stability. The inductor's maximum current capability must be adequate enough to handle the peak current at the worst case condition. Additionally if an inductor core is chosen with too low a current rating, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and overheating in the core. The series resistance, DCR, within the inductor causes conduction loss and heat dissipation. A shielded inductor is usually more suitable for EMI susceptible applications, such as LED backlighting. The peak current can be derived from the voltage across the inductor during the Off-period, as expressed in Equation 11:
IL peak = ( V O x I O ) ( 85% x V I ) + 1 2 [ V I x ( V O - V I ) ( L x V O x f SW ) (EQ. 11)
Input Capacitor
Switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. This reduces interaction between the regulator and input supply, thereby improving system stability. The high switching frequency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. A capacitor with low internal series resistance should be chosen to minimize heating effects and improve system efficiency, such as X5R or X7R ceramic capacitors, which offer small size and a lower value of temperature and voltage coefficient compared to other ceramic capacitors.
The choice of 85% is just an average term for the efficiency approximation. The first term is the average current, which is inversely proportional to the input voltage. The second term is the inductor current change, which is inversely proportional to L and fSW. As a result, for a given switching.
REGISTER 0x00 BRT7 BRT6
PWM BRIGHTNESS CONTROL REGISTER BRT5 BRT4 BRT3 BRT2 BRT1 BRT0
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) BIT ASSIGNMENT BRT[7..0] BIT FIELD DEFINITIONS = 256 steps of PWM brightness levels FIGURE 30. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER
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REGISTER 0x01 RESERVED Bit 7 (R/W) DEVICE CONTROL REGISTER RESERVED Bit 3 (R/W) PWM_MD PWM_SEL BL_CTL
RESERVED RESERVED RESERVED Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W)
Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
BIT ASSIGNMENT PWM_MD PWM_SEL BL_CTL
BIT FIELD DEFINITIONS = PWM mode select bit (1 = absolute brightness, 0 = % change) default = 0 = Brightness control select bit (1 = control by PWMI, 0 = control by SMBus) default = 0 = BL On/Off (1 = On, 0 = Off) default = 0 FIGURE 31. DESCRIPTIONS OF DEVICE CONTROL REGISTER
REGISTER 0x02 RESERVED Bit 7 (R) BIT Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FAULT/STATUS REGISTER 2_CH_SD Bit 5 (R) 1_CH_SD Bit 4 (R) BL_STAT Bit 3 (R) OV_CURR THRM_SHDN Bit 2 (R) Bit 1 (R) FAULT Bit 0 (R)
RESERVED Bit 6 (R)
BIT ASSIGNMENT 2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN FAULT
BIT FIELD DEFINITIONS = Two LED output channels are shutdown (1 = shutdown, 0 = OK) = One LED output channel is shutdown (1 = shutdown, 0 = OK) = BL Status (1 = BL On, 0 = BL Off) = Input Overcurrent (1 = Overcurrent condition, 0 = Current OK) = Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK) = Fault occurred (Logic "OR" of all of the fault conditions)
FIGURE 32. DESCRIPTIONS OF FAULT/STATUS REGISTER REGISTER 0x03 LED PANEL Bit 7 = 1 ID REGISTER
MFG3 Bit 6 (R)
MFG2 Bit 5 (R)
MFG1 Bit 4 (R)
MFG0 Bit 3 (R)
REV2 Bit 2 (R)
REV1 Bit 1 (R)
REV0 Bit 0 (R)
BIT ASSIGNMENT MFG[3..0]
BIT FIELD DEFINITIONS = Manufacturer ID. See "Identification Register (0x03)" on page 19. Data 0 to 8 in decimal correspond to other vendors data 9 in decimal represents Intersil ID data 10 to 14 in decimal are reserved data 15 in decimal Manufacturer ID is not implemented = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins) FIGURE 33. DESCRIPTIONS OF ID REGISTER
REV[2..0]
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 11/13/09 REVISION FN6996.1 CHANGE Changed in OVP and VOUT Requirement Changed from: VOUT can only regulate between 61% and 100% of the VOUT_OVP such that: To: VOUT can only regulate between 64% and 100% of the VOUT_OVP such that From: Allowable VOUT = 61% to 100% of VOUT_OVP To: Allowable VOUT = 64% to 100% of VOUT_OVP From: ...then the VOUT is allowed to operate between 24.4V and 40V. To: ...then the VOUT is allowed to operate between 25.6V and 40V. From: ...should follow VOUT = (61% ~100%)OVP requirement To: ...should follow VOUT = (64% ~100%)OVP requirement. Changed VSC spec from "2.5Vmin, 3.4Vmax, 3.3min, 4.4max, 4.2min, 5.4max to "2.4Vmin, 3.6Vmax, 3.3min, 4.6max, 4.2min, 5.6max". Initial Release.
10/21/09
FN6996.0
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL97677 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 22
FN6996.1 November 13, 2009
ISL97677
Package Outline Drawing
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 11/07
4X 3.5 5.00 A B 6 PIN 1 INDEX AREA 28X 0.50 6 PIN #1 INDEX AREA
25 24
32 1
5.00
3 .30 0 . 15
17
(4X) 0.15 16 9
8
0.10 M C A B 4 32X 0.23 - 0.05
+ 0.07
32X 0.40 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0.1
C
BASE PLANE
SEATING PLANE 0.08 C
( 4. 80 TYP ) ( 3. 30 )
( 28X 0 . 5 )
SIDE VIEW
(32X 0 . 23 )
C ( 32X 0 . 60)
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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FN6996.1 November 13, 2009

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